The present invention generally relates to semiconductor integrated circuits (“ICs”) assembly and, more particularly, to an image sensor packaging structure and a method of manufacturing the same.
One of the important processes at the final stage of fabricating semiconductor integrated circuits (“ICs”) is multi-leveled packaging, which includes expanding the pitch between electrodes of an IC chip for subsequent processing. The multi-leveled packaging protects an IC chip from internal or external stress, provides thermal paths for dissipating heat generated within the chip, and forms electronic interconnections. The method for packaging an IC chip may concern the overall cost of the IC, and in addition, may affect the performance and reliability of the IC and in turn the system using the IC.
Packaged IC chips may be generally divided into two types, that is, hermetic package and non-hermetic package. A hermetic-package IC chip refers to one isolated from an external environment by, for example, a vacuum-tight enclosure. The material for a hermetic package may typically include ceramic, which is suitable for high-performance applications such as image sensors or pressure sensors. A non-hermetic-package IC chip, on the other hand, refers to one not completely isolated from an external environment. The manufacturing cost of a hermetic package is higher than that of a non-hermetic package. Recent advances in hermetic package include the use of plastic material, which has expanded the field of application and enhanced the performance capability of hermetic package. Plastic packages are cost-effective due to the use of automated batch-handling in their manufacturing processes.
A recent development in assembly technique is ball grid array (“BGA”) package, which is applicable to both ceramic and plastic packages and includes various types of internal package structures. A BGA package uses multiple solder balls or bumps for electrical, mechanical and thermal interconnections between an IC chip and other microelectronic devices. Solder bumps function to mechanically secure an IC chip to a circuit board and electrically connect the IC chip to a conductor pattern formed on the circuit board. The BGA technique is known as one belongs to the Controlled Collapse Chip Connection (C4) or flip-chip technology.
The flip chip technology may be used in conjunction with various types of circuit boards, including ceramic substrates, printed wiring boards, flexible circuits and silicon substrates. The solder bumps, typically arranged in an array surrounding a flip chip, are formed on electrically conductive bond pads which in turn electrically interconnect the circuitry of the flip chip. A relatively large number of solder bumps are often required to support the functions performed by the circuitry of the flip chip. As an example of a flip chip having a size of approximately thirteen millimeters per side, the large number of solder bumps are crowded along the perimeter of the chip with their conductors being spaced apart from each other by a pitch of approximately 0.1 millimeter or less.
FIG. 1 is a schematic diagram of a section of a conventional flip chip 26. Referring to FIG. 1, flip chip 26 includes a solder bump 10 soldered directly to an upper surface of a bump pad 14, which has a rectangular shape, as shown in FIG. 1A, and is partially covered by a passivation layer 12 of, for example, SiN or SiO2. A circular pad opening 13 formed in passivation layer 12 exposes bump pad 14 on which solder bump 14 is formed. Bump pad 14 is surrounded by a dielectric layer 15 such as an oxide layer formed in flip chip 26. Bump pad 14 forms an electrical contact with an upper conductive layer 16, which is separated from underlying conductive layers 22 by an insulative layer 18. Upper and underlying conductive layers 16 and 22 are electrically connected to each another through conductive vias 20 extending through insulative layers 18. Insulative layers 18 and underlying conductive layers 22 are sequentially deposited over a silicon chip substrate 24 by a conventional technique during semiconductor fabrication.
After solder bumps 10 are formed, flip chip 26 is flipped over to allow solder bumps 10 to be bonded to electrical terminals disposed on another substrate such as a printed circuit board (“PCB”). Referring to FIG. 1B, solder bumps are formed on flip chip 26 in rows and columns. Empty spaces 11 are provided in the rows and columns to allow for the configuration of ICs formed on silicon chip substrate 24. After solder bumps 10 are bonded to a PCB substrate 28, flip chip 26 is subjected to a variety of tests such as bump shear tests and die shear tests by applying shear stress thereto in order to determine the mechanical integrity of electrical connections formed between flip chip 26 and PCB substrate 28. Furthermore, flip chip 26 may be subjected to temperature tests of approximately 150° C. For high-performance electronic devices such as CCD (Charged Coupled Device) image sensors or CMOS (Complementary Metal-Oxide-Semiconductor) image sensors, however, leadless chip carrier packages may be more commonly used than flip chip packages.
A CCD image sensor refers to an electronic device capable of transforming a light pattern or image into an electric charge pattern or electronic image. A CCD includes several photosensitive elements for collecting, storing and transporting electrical charge from one photosensitive element to another. With its photosensitive properties, silicon is a suitable material in the design of image sensors. Each of the photosensitive elements represents a picture element or pixel. In accordance with semiconductor technology and design rules, the pixels in structure are generally formed in lines or matrices. At least one output amplifier provided at a side of an image sensor chip collects signals from the CCD. An electronic image is obtained by applying to the at least one output amplifier a series of pulses, which transfer the charge of a pixel one after another, line after line. The at least one output amplifier converts the charge into a voltage signal. External electronics transform the voltage signal into one suitable for use in monitors or frame grabbers.
A CMOS image sensor operates at a lower voltage level than a CCD image sensor, and therefore is suitable for portable applications due to lower power consumption. Each CMOS active sensor cell, which can be addressed and read individually, includes a buffer amplifier and generally four transistors and a photo-sensing element. Each sensor cell also includes a transfer gate separating a photo sensor from a capacitive “floating diffusion”, a source-follower transistor to buffer the floating diffusion from readout-line capacitance, and a row-select gate to connect the cell to the readout line. All of the pixels disposed in a column are connected to a sense amplifier. In addition to the advantage of lower power consumption, a CMOS image sensor generally has a less complicated design than a CCD image sensor, and therefore requires less support circuitry than a CCD image sensor.
FIG. 1C is a cross-sectional diagram of a conventional leadless chip carrier package 30. Referring to FIG. 1C, leadless chip carrier package 30, generally used to package a CCD or CMOS image sensor IC chip, includes a layer of transparent cover glass 32 provided on a support layer 35. An anti-reflective coat 34 is provided between cover glass 32 and support layer 35. A multi-layered substrate 36 includes a castellation 42 on which an image sensor die 38 is located. Top leads 40, extending from die 38, are disposed in electrical contact with bottom leads 44, which wrap around sides and a partial bottom surface of multi-layered substrate 36. Transparent cover glass 32 facilitates the transmission of light toward image sensor die 38.
Leadless chip carrier package 30, which may have a thickness 46 of approximately 2 mm (millimeter), if used to package an image sensor, may disadvantageously consume a relatively large space, resulting in an unduly large image sensor device and in turn an excessively large module including such an image sensor and other electronic devices. It is therefore desirable to provide a structure and method for packaging an image sensor and a module in an acceptable profile.